SDA6000 Datasheet, PDF (218/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
7.3.4.2 Baud Rate Selection and Calculation
The autobaud detection requires some calculations concerning the programming of the
baud rate generator and the baud rates to be detected. Two steps must be considered:
• Defining the baud rate(s) to be detected
• Programming of the baud rate timer prescaler - setup of the clock rate of f_DIV
In general, the baud rate generator of the ASC in asynchronous mode is built up of two
parts:
• the clock prescaler part which derives f_DIV from f_MOD
• the baud rate timer part which generates the sample clock f_BRT and the baud rate clock
f_BR
Prior to an autobaud detection, the prescaler part has to be set up by the CPU while the
baud rate timer (register BG) is automatically initialized with a 13-bit value (BR_VALUE)
after a successfull autobaud detection. For the subsequent calculations, the fractional
divider is used (CON_FDE = 1).
Note: It is also possible to use the fixed divide-by-2 or divide-by-3 prescaler. But the
fractional divider allows for a more precise adaption of f_DIV to the required value.
Standard Baud Rates
For standard baud rate detection the baud rates as shown in Table 7-20 can be
detected. Therefore, the output frequency f_DIV of the ASC baud rate generator must be
set to a frequency derived from the system, clocked (33 MHz) in a way that it is equal to
11.0592 MHz. The value to be written into register FDV is the nearest integer value
which is calculated according the following formula:
FDV = ^{512 × 11.0592 MHz}
33 MHz
Table 7-20 defines the nine standard baud rates (Br0 - Br8) which can be detected for
f_DIV = 11.0592 MHz.
Users Manual
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2000-06-15