SDA6000 Datasheet, PDF (278/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Sync System
H-Sync Delay
(SDH)
Vertical Blacklevel Clamping
Screen Background Area
Pixel Layer 1
Pixel
Layer 2
Variable Width
V-Sync
Delay
(SDV)
Variable
Height
t _{H_clmp_b}
(BHCR)
t _{H_clmp_e}
(EHCR)
H-Sync
t_{H_period (HPR)}
UET11168
Figure 9-1 M2’s Display Timing
Blacklevel Clamping Area
During horizontal and vertical blacklevel clamping, the black value (RGB = 000) is
delivered. The blank pin is set to ‘1’ and COR is set to ‘0’ (normal polarity assumed). This
area is vertically programmable (in terms of lines) and horizontally in terms of 33.33 MHz
clock cycles. These programmings are independent of all other registers.
Screen Background Area
The size of that area is defined by the sync delay registers (SDH and SDV) and the size
of pixel layer1. The contents of that area are defined by GA instruction SAR (refer also
to Chapter 10.1). Pixels within that area are programmable (colour and transparency
level), but all have the same value.
Users Manual
9-4
2000-06-15