SDA6000 Datasheet, PDF (215/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
Figure 7-34 shows how the autobaud detection unit of the ASC is integrated into its
asynchronous mode configuration. The RXD data line is an input of the autobaud
detection unit. The clock f_DIV, which is generated by the fractional divider, is used by the
autobaud detection unit as a time base. After successful recognition of the baud rate and
asynchronous operating mode of the RXD data input signal, bits in the CON register and
the value of the BG register in the baud rate timer are set to the appropriate values, and
the ASC_P3 can start immediately with the reception of serial input data.
Asynchronous Mode
f
f
Prescaler/
DIV
MOD
Fractional Divider
Baud Rate
Timer
Autobaud
Detection
Serial Port
Control
RxD
Receive/Transmit
MUX
IrDA
Decoding
Buffers and
Shift Registers
MUX
TxD
IrDA
Coding
UEB11153
Figure 7-34 ASC_P3 Asynchronous Mode Block Diagram
The following sequence must be generally executed to start the operation of the
autobaud detection unit:
• Definition of the baud rates to be detected: standard or non-standard baud rates
• Programming of the Prescaler/Fractional Divider to select a specific value of f_DIV
• Starting the Prescaler/Fractional Divider (setting CON_R)
• Preparing the interrupt system of the CPU
• Enabling the autobaud detection (setting ABCON_ EN and the interrupt enable bits in
ABCON for interrupt generation, if required)
• Polling interrupt request flag or waiting for the autobaud detection interrupt
7.3.4.1 Serial Frames for Autobaud Detection
The autobaud detection of the ASC_P3 is based on the serial reception of a specific
two-byte serial frame. This serial frame is build up by the two ASCII bytes ‘at’ or ‘AT’ (‘aT’
or ‘At’ are not allowed). Both byte combinations can be detected in five types of
asynchronous frames. Figure 7-35 and Figure 7-36 show the serial frames which are
least detected.
Users Manual
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2000-06-15