SDA6000 Datasheet, PDF (360/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Register Overview
Name
RL0
RH0
RL1
RH1
RL2
RH2
RL3
RH3
RL4
RH4
RL5
RH5
RL6
RH6
RL7
RH7
Physical 8-Bit
Description
Address Address
(CP) + 0 F0_H
(CP) + 1 F1_H
(CP) + 2 F2_H
(CP) + 3 F3_H
(CP) + 4 F4_H
(CP) + 5 F5_H
(CP) + 6 F6_H
(CP) + 7 F7_H
(CP) + 8 F8_H
(CP) + 9 F9_H
(CP) + 10 FA_H
(CP) + 11 FB_H
(CP) + 12 FC_H
(CP) + 13 FD_H
(CP) + 14 FE_H
(CP) + 15 FF_H
CPU General Purpose (Byte) Register RL0
CPU General Purpose (Byte) Register RH0
CPU General Purpose (Byte) Register RL1
CPU General Purpose (Byte) Register RH1
CPU General Purpose (Byte) Register RL2
CPU General Purpose (Byte) Register RH2
CPU General Purpose (Byte) Register RL3
CPU General Purpose (Byte) Register RH3
CPU General Purpose (Byte) Register RL4
CPU General Purpose (Byte) Register RH4
CPU General Purpose (Byte) Register RL5
CPU General Purpose (Byte) Register RH5
CPU General Purpose (Byte) Register RL6
CPU General Purpose (Byte) Register RH6
CPU General Purpose (Byte) Register RL7
CPU General Purpose (Byte) Register RH7
Reset
Value
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
XX_H
13.3
Registers Ordered by Context
The following table lists all SFRs which are implemented in the M2 grouped by their
context. Their actual address can be seen in the next chapter.
Table 13-1
Name
Description
SSC Registers
SSCCON Control Register
SSCBR Baud Rate Timer Reload Register
SSCTB
Transmit Buffer Register
SSCRB Receive Buffer Register
ASC Registers
S0CON Control Register
Physical 8-Bit Reset
Address Address Value
FFB2_H D9_H
F0B4_H 5A_H
F0B0_H 58_H
F0B2_H 59_H
FFB0_H D8_H
0000_H
0000_H
0000_H
0000_H
0000_H
Users Manual
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2000-06-15