SDA6000 Datasheet, PDF (353/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Slicer and Acquisition
Bit
FCSEL
VCR
Function
There are three different framing codes which can be used for each field.
The framing code used for the actual line is selected with FCSEL
(corresponds to slicer 1).
FCSEL
00
01
10
11
FC
FC1
FC2
FC3
No FC-check (all data are dumped to the VBI buffer)
This bit is used to change the behavior of the D-PLL and H-PLL.
0: D-PLL tuning is stopped after CRI; H-PLL -> slow time constant
1: D-PLL is tuned throughout the line; H-PLL -> fast time constant
ACQLP3
Reset Value: XXXX_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLSS
SSL(6..0)
Bit
SLSS
SSL(6 … 0)
Function
Slicing Level Source Selector
The slicer allows the use of an internal calculated slicing level or an
external set slicing level.
0: Internal calculated slicing level is used.
1: External set slicing level is used.
Set Slicing Level
If the bit SLSS is set the slicer is using the value of SSL as slicing level
instead of the internal calculated slicing level. The slicing level output in
parameter MSL is never the less the internal calculated value.
Users Manual
12 - 22
2000-06-15