SDA6000 Datasheet, PDF (60/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
C16X Microcontroller
3rd –>EXECUTE:
In this stage an operation is performed on the previously fetched operands in the ALU.
In addition, the condition flags in the PSW register are updated, as specified by the
instruction. All explicit writes to the SFR memory space and all auto-increment or auto-
decrement writes to GPRs used as indirect address pointers are also performed during
the execute stage of an instruction.
4th –>WRITE BACK:
In this stage all external operands and the remaining operands within the internal RAM
space are written back.
A particularity of the CPU are the so-called imported instructions. These imported
instructions are internally generated by the machine to provide the time needed to
process instructions which cannot be processed within one machine cycle. They are
automatically imported into the decoding stage of the pipeline, and then they pass
through the remaining stages like all standard instructions. Program interrupts are also
performed by means of imported instructions. Although these internally imported
instructions will not be noticed in reality, they are introduced here to ease the explanation
of the pipeline in the following:
Sequential Instruction Processing
Each single instruction has to pass through each of the four pipeline stages regardless
of whether all possible stage operations are performed or not. Since passing through
one pipeline stage takes at least one machine cycle, any isolated instruction takes at
least four machine cycles to be completed. Pipelining, however, allows parallel (i.e.
simultaneous) processing of up to four instructions. Thus, most of the instructions seem
to be processed during one machine cycle as soon as the pipeline has been filled once
after reset (see Figure 4-11).
Instruction pipelining increases the average instruction throughput considered over a
certain period of time. In the following, any execution time specification of an instruction
always refers to the average execution time due to pipelined parallel instruction
processing.
Users Manual
4 - 27
2000-06-15