SDA6000 Datasheet, PDF (100/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Interrupt and Trap Functions
Note: PEC transfers are only executed if their priority level is higher than the CPU level,
i.e. only PEC channels 7 … 4 are processed, while the CPU executes on level 14.
All interrupt request sources that are enabled and programmed for PEC service
should use different channels. Otherwise only one transfer will be performed for
all simultaneous requests. When COUNT is decremented to 00_H, and the CPU is
interrupted, an incorrect interrupt vector will be generated.
Channel Link Mode for Data Chaining
Data chaining with linked PEC channels is enabled if the channel link control bit in
PECCx register is set to ‘1’ either in one or both PEC channel control registers of a
channel pair. In this case, two PEC channels are linked together and handle chained
block transfers alternatively to each other. The whole data transfer is divided into several
block transfers where each block is controlled by one PEC channel of a channel pair.
When a data block is completely transferred a channel link interrupt is generated and
the PEC service request processing is automatically switched to the “other” PEC
channel of the channel-pair. Thus, PEC service requests addressed to a linked PEC
channel are either handled by linked PEC channel A or by linked PEC channel B. This
channel toggle allows the setting up of shadow and multiple buffers for PEC transfers by
changing pointer and count values of one channel while the other channel is active. The
following table lists the channels that can be linked together, and the channel numbers
to address the linked channels.
Linked PEC Channels
PEC Channel
A
PEC Channel
B
channel 0
channel 1
channel 2
channel 3
channel 4
channel 5
channel 6
channel 7
Linked PEC Channel
channel 0
channel 2
channel 4
channel 6
For each pair of linked channels an internal channel flag, the channel link toggle flag
CLT, identifies which of the two PEC channels will serve the next PEC request. The CLT
flag is indicated in both PECCx registers of the two linked PEC channels, where the CLT
bit in channel B is always inverse to the CLT bit in channel A. The very first transfer is
always started with the channel A if the CLT bit is not otherwise programmed before. The
CLT bit is only valid in the case of linked PEC channels, indicated by the CL bits of linked
channels. If linking is not enabled, the CLT bit of both channels is always zero.
The internal channel link flag CLT toggles, and the other channel begins servicing with
the next request if the “old” channel stops the service (COUNT = 0), and if the new
Users Manual
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2000-06-15