SDA6000 Datasheet, PDF (350/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Slicer and Acquisition
Bit
ACCUON
PLLLON
LOWPON
PFILLON
GDPON
GDNON
FREON
NOION
Function
Accumulator on
Improves slicing level calculation under noisy conditions.
If noise has been detected during automatic mode or if the bit NOION
has been set the internal slicing level calculation can be improved by
setting this bit.
0: Standard slicing level calculation
1: Improved slicing level calculation (improvement depends also on
parameter ALENGTH)
PLL tune on
If noise has been detected during automatic mode or if the bit NOION
has been set the data clock recovery PLL can be tuned throughout the
line by setting this bit.
0: PLL is frozen after clock run in
1: PLL is tuned throughout the line
Low Pass On
If noise has been detected during automatic mode or if the bit NOION
has been set a special low pass can be switched into the signal pass by
setting this bit (useful if mainly high frequency noise above 3.5 MHz is
present).
0: Low pass is not used
1: Low pass is used
Pre Filter On
If noise has been detected during automatic mode or if the bit NOION
has been set a second filter can be switched into the signal pass by
setting this bit (also useful if mainly high frequency noise above 3.5 MHz
is present).
0: Low pass is not used.
1: Low pass is used.
0: Group delay compensation depends on AGDON
1: Positive group delay compensation is always on
0: Group delay compensation depends on AGDON
1: Negative group delay compensation is always on
0: Frequency depending attenuation compensation depends on
AFRON
1: Frequency depending attenuation compensation is always on
0: Noise compensation depends on ANOON
1: Noise compensation is always on
Users Manual
12 - 19
2000-06-15