SDA6000 Datasheet, PDF (92/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Interrupt and Trap Functions
Interrupt Control Registers
All interrupt control registers are organized identically. The lower 8 bits of an interrupt
control register contain the complete interrupt status information of the associated
source which is required during one round of prioritization; the upper 8 bits of the
respective register are reserved. All interrupt control registers are bit-addressable and
all bits can be read or written via software. This allows each interrupt source to be
programmed or modified with just one instruction. When accessing interrupt control
registers through instructions which operate on word data types, their upper 8 bits
(15 … 8) will return zeros when read, and will discard written data.
Note: The layout of the Interrupt Control registers shown below applies to each xxIC
register, where xx stands for the mnemonic for the respective source.
Interrupt Node Sharing
The interrupt controller of M2 can be configured to control up to 33 different sources. If
there is a need for a greater number of interrupt sources to be managed, interrupt
requests may share the same interrupt node. In this case, all the sources on the same
node share the priority level defined by the corresponding Interrupt Control register xxIC
and may be globally enabled/disabled by the IE bit of this register.
Arbitration between sources connected to the same node must be performed by the
interrupt handler associated with this node. For low rate requests, the software overhead
is not critical.
Users Manual
5-8
2000-06-15