 English |
|
|
|
|
|
|
|
| SDA6000 Datasheet, PDF (202/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller | |||
| |||
| ◁ |
SDA 6000
7.3.1.1 Asynchronous Data Frames
Peripherals
8-Bit Data Frames
8-bit data frames either consist of 8 data bits D7 ⦠D0 (S0M = â001Bâ), or of 7 data bits
D6 ⦠D0 plus an automatically generated parity bit (S0M = â011Bâ). Parity may be odd
or even, depending on bit S0ODD in register S0CON. An even parity bit will be set, if the
modulo-2-sum of the 7 data bits is â1â. An odd parity bit will be cleared in this case. Parity
checking is enabled via bit S0PEN (always OFF in 8-bit data mode). The parity error flag
S0PE will be set along with the error interrupt request flag, if a wrong parity bit is
received. The parity bit itself will be stored in bit S0RBUF.7.
SOM = 001B
10-/11-Bit UART Frame
8 Data Bits
0
1
1
Start D0
Bit LSB
D1
D2
D3
D4
D5
D6
D7
MSB
(1st)
Stop
Bit
(2nd)
Stop
Bit
SOM = 011B
10-/11-Bit UART Frame
7 Data Bits
0
1
1
Start D0
Bit LSB
D1
D2
D3
D4
D5
D6 Parity
MSB Bit
(1st)
Stop
Bit
(2nd)
Stop
Bit
UED11144
Figure 7-25 Asynchronous 8-Bit Frames
9-Bit Data Frames
9-bit data frames either consist of 9 data bits D8 ⦠D0 (S0M = â100Bâ), of 8 data bits
D7 ⦠D0 plus an automatically generated parity bit (S0M = â111Bâ) or of 8 data bits
D7 ⦠D0 plus wake-up bit (S0M = â101Bâ). Parity may be odd or even, depending on bit
S0ODD in register S0CON. An even parity bit will be set, if the modulo-2-sum of the
8 data bits is â1â. An odd parity bit will be cleared in this case. Parity checking is enabled
via bit S0PEN (always OFF in 9-bit data and wake-up mode). The parity error flag S0PE
will be set along with the error interrupt request flag, if a wrong parity bit is received. The
parity bit itself will be stored in bit S0RBUF.8.
Users Manual
7 - 51
2000-06-15
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese