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| SDA6000 Datasheet, PDF (275/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller | |||
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SDA 6000
Clock System
Note: Register SYSCON2 cannot be changed after execution of the EINIT instruction.
PFR
Reset Value: 0148H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-
-
-
-
-
-
PF(10..0)
rw
Bit
Function
PF (10 ⦠0)
Pixel Frequency Factor
This register defines the relation between the output pixel frequency and
the frequency of the crystal. The pixel frequency does not depend on the
line frequency. It can be calculated by the following formula:
fPIX = PF Ã 300 MHz / 8192
The pixel frequency can be adjusted in steps of 36.6 KHz.
After power-on, this register is set to 328D. So, the default pixel
frequency is set to 12.01 MHz.
Note: Register values exceeding 1366 generate pixel frequencies
which are outside of the specified boundaries.
Users Manual
8-5
2000-06-15
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