SDA6000 Datasheet, PDF (285/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Sync System
Clamp Phase Area
Screen Background Area
Pixel Layer Area
Video
H Period - Frame n
H Pulse
UED11169
Figure 9-2 Priority of Clamp Phase, Screen Background and Pixel Layer Area
BVCR
Reset Value: 0000_H
BVCR1
BVCR0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-
-
-
-
-
-
BVCR(9..0)
rw
Bit
BVCR
(9 … 0)
Function
Beginning of Vertical Clamp Phase. (Master and slave mode).
This register defines the beginning of the vertical clamp phase from the
positive edge of the vertical sync impulse (at normal polarity) in line
count.
Users Manual
9 - 11
2000-06-15