SDA6000 Datasheet, PDF (121/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
System Control & Configuration
Reset conditions are indicated in the WDTCON register.
Hardware Reset
A hardware reset is triggered asynchronously by a falling edge of the reset input signal,
RSTIN. To ensure the recognition of the RSTIN signal, it must be held low for at least
2 CPU clock cycles, assuming the clock input signal is stable. Also, shorter RSTIN
pulses may trigger a hardware reset, however, this is not recommended. The internal
reset condition is prolonged until one of the following conditions arises:
• the rising edge of the RSTIN signal, or
• the termination of the reset sequence, if RSTIN was deasserted before, or
• the termination of the lengthening conditions.
After termination of the reset state, program execution will start.
Three different kinds of hardware reset conditions are considered:
• Power-on Reset
A complete power-on reset requires an active RSTIN time until a stable clock signal
is available. The on-chip oscillator needs about 2 ms to stabilize.
• Long Hardware Reset
A long hardware reset requires an RSTIN active time longer than the duration of the
internal reset sequence. The duration of the internal reset sequence is 2056 TCL.
After the internal reset sequence has been completed, the RSTIN input is sampled.
As long as the reset input is still active the internal reset condition is prolonged.
Accordingly, the internal hardware reset (HWRST) is active until the external reset on
the RSTIN input becomes inactive.
Note: The hardware reset is also used as a wake up from power down state; in this case
the internal system reset will be lengthened (execution of 1. instruction delayed)
until the oscillator and PLL have been stabilized.
• Short Hardware Reset
The RSTIN active time of a short hardware reset is between 16 TCL and 2056 TCL.
If the RSTIN signal is active for at least 16 TCL clock cycles the internal reset
sequence is started (see below). In case of a short HW-reset, the internal HWRST
signal is prolonged until the reset sequence is finished.
Software Reset
The reset sequence can be triggered at any time via the protected instruction SRST
(Software Reset). This instruction can be executed deliberately within a program, e.g. to
leave bootstrap loader mode, or upon a hardware trap that reveals a system failure.
Watchdog Timer Reset
When the watchdog timer is not disabled during the initialization or serviced regularly
during program execution it will overflow and trigger the reset sequence. Other than
Users Manual
6-4
2000-06-15