SDA6000 Datasheet, PDF (108/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Interrupt and Trap Functions
All instructions in the pipeline, including instruction N (during which the interrupt request
flag is set), are completed before entering the service routine. The actual execution time
for these instructions (e.g. wait-states) therefore influences the interrupt response time.
In Figure 5-4 the respective interrupt request flag is set in cycle 1 (the fetching of
instruction N). The indicated source wins the prioritization round (during cycle 2). In
cycle 3 a TRAP instruction is injected into the decode stage of the pipeline, replacing
instruction N+1 and clearing the source's interrupt request flag to ‘0’. Cycle 4 completes
the injected TRAP instruction (save PSW, IP and CSP, if in segmented mode) and
fetches the first instruction (I1) from the respective vector location.
All instructions that entered the pipeline, after the setting of the interrupt request flag
(N+1, N+2), will be executed after returning from the interrupt service routine.
The minimum interrupt response time is 5 states (10 TCL). This requires program
execution from the internal code memory, no external operand read requests and setting
the interrupt request flag during the last state of an instruction cycle. When the interrupt
request flag is set during the first state of an instruction cycle, the minimum interrupt
response time under these conditions is 6 state times (12 TCL).
The interrupt response time is increased by all delays of the instructions in the pipeline
that are executed before entering the service routine (including N).
• When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, or
when instruction N explicitly writes to the PSW or the SP, the minimum interrupt
response time may be extended by 1 state time for each of these conditions.
• When instruction N reads an operand from the internal code memory, or when N is a
call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum interrupt
response time may be extended by 2 state times during internal code memory
program execution.
• In case instruction N reads the PSW and instruction N-1 effects the condition flags,
the interrupt response time may be extended by 2 state times.
The worst case interrupt response time during internal code memory program execution
adds 12 state times (24 TCL).
Any reference to external locations increases the interrupt response time due to pipeline
related access priorities. The following conditions have to be considered:
• Instruction fetch from an external location
• Operand read from an external location
• Result write-back to an external location
There are a number of combinations depending on where the instructions, source and
destination operands are located. Note, however, that only access conflicts contribute to
the delay.
A few examples illustrate these delays:
• The worst case interrupt response time, including external accesses, will occur when
instructions N, N+1 and N+2 are executed out of external memory, instructions N-1
Users Manual
5 - 24
2000-06-15