SDA6000 Datasheet, PDF (246/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
7.4.7 Register Description
The operating mode of the serial channel SSC0 is controlled by its control register
SSCCON. This register contains control bits for mode and error check selection, and
status flags for error identification. Depending on bit SSC0EN, either control functions or
status flags and master/slave control is enabled.
SSC0EN = 0: Programming Mode
SSCCON
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC0 SSC0 - SSC0 SSC0 SSC0 SSC0 SSC0 SSC0 SSC0 SSC0 SSC0
EN MS
AREN BEN PEN REN TEN LB PO PH HB
rw rw
rw rw rw rw rw rw rw rw rw
SSC0BM
rw
Bit
SSC0BM
SSC0HB
SSC0PH
SSC0PO
SSC0LB
SSC0TEN
SSC0REN
Function
SSC0 Data Width Selection
0:
Reserved. Do not use this combination.
1 … 15: Transfer Data Width is 2 … 16 bit (<SSC0BM>+1)
SSC0 Heading Control Bit
0: Transmit/Receive LSB First
1: Transmit/Receive MSB First
SSC0 Clock Phase Control Bit
0: Shift transmit data on the leading clock edge, latch on trailing edge
1: Latch receive data on leading clock edge, shift on trailing edge
SSC0 Clock Polarity Control Bit
0: Idle clock line is low, leading clock edge is low-to-high transition
1: Idle clock line is high, leading clock edge is high-to-low transition
SSC0 Loop Back Bit
0: Normal output
1: Receive input is connected with transmit output (half duplex mode)
SSC0 Transmit Error Enable Bit
0: Ignore transmit errors
1: Check transmit errors
SSC0 Receive Error Enable Bit
0: Ignore receive errors
1: Check receive errors
Users Manual
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2000-06-15