SDA6000 Datasheet, PDF (263/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
Field
CO
WM
Bits Type
10..8 rw
[15:8] wh
Value Description
Counter of Transmitted Bytes Since Last
Data Interrupt. If a multi byte transmission
could not be finished because of a missing
acknowledge, the number of correctly
transferred bytes can be read from CO. It is
automatically set to zero by the correct
number (defined by CI) of write/read
accesses to the buffers ICRTB0 … 3.
000 No Byte
001 1 Byte
010 2 Bytes
011 3 Bytes
100 4 Bytes
The number of legal bytes depends on the
data buffer size (CI). Writing to this bit field
does not affect its content.
If WMEN is set, WM is mirrored here.
–
Write Mirror
If WMEN is set, RTB0 may be written here.
Reading WM will result in zero.
1) _{While IRQD, IRQP or IRQE is set and the I}2_{C module is in master mode or has been selected as a slave, the}
I²C clock line is held low which prevents further transfers on the I²C bus.
The clock line of the I²C bus is released when IRQD, IRQE and IRQP are cleared. Only in this case can the
next I²C bus action take place.
Interrupt request bits may be set or cleared via software, e.g. to control the I²C bus.
Users Manual
7 - 112
2000-06-15