SDA6000 Datasheet, PDF (169/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
Auxiliary Timer in Capture Mode
Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the
respective register TxCON to ‘101_B’. In capture mode the contents of the core timer are
latched into an auxiliary timer register in response to a signal transition at the respective
auxiliary timer’s external input line TxIN. The capture trigger signal can be a positive, a
negative, or both a positive and a negative transition.
The two least significant bits of bit field TxI are used to select the active transition (see
table in the counter mode section), while the most significant bit, TxI.2, is irrelevant for
capture mode. It is recommended to keep this bit cleared (TxI.2 = ‘0’).
Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4)
stops independent of its run flag T2R or T4R.
Edge
Select
TxIN
Capture Register Tx
x = 2, 4
Interrupt
Request
TxI
Input
Clock
Core Timer T3
Up/Down
T3OTL
Interrupt
Request
T3OUT
T3OE
UES11204
Figure 7-13 Auxiliary Timer of Timer Block 1 in Capture Mode
Upon a trigger (selected transition) at the corresponding input line TxIN the contents of
the core timer are loaded into the auxiliary timer register and the associated interrupt
request flag TxIR will be set.
Note: The direction control for T2IN and for T4IN must be set to ‘Input', and the level of
the capture trigger signal should be kept high or low for at least 4 f_{hw_clk}
(BPS1 = ‘01’) cycles before it changes, to ensure correct edge detection.
Users Manual
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2000-06-15