SDA6000 Datasheet, PDF (368/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Register Overview
Table 13-1 (cont’d)
Name
Description
EXICON External Interrupt Control
OSCCON Oscillator Pad Control Register
IDMANUF Manufacture ID
IDCHIP
Chip ID
TM_LO
Hardware Testmode Register Low
TM_HI
Hardware Testmode Register High
FOCON SCU Register (no Function within M2)
SYSCON3 SCU Register (no Function within M2)
1) _{OCDS related registers that are not reset during a controller reset.}
2) _{No 8-bit addresses provided for XBUS registers.}
Physical 8-Bit Reset
Address Address Value
F1C0_H E0_H
F1C4_H E2_H
F07E_H 3F_H
F07C_H 3E_H
FEFC_H 7E_H
FEFE_H 7F_H
FFAA_H D5_H
F1D4_H EA_H
0000_H
0001_H
XXXX_H
XXXX_H
0000_H
0000_H
0000_H
0000_H
13.4
Registers Ordered by Address
The following tables summarize the register symbols and their “short addresses”. The
physical address can be calculated by multiplying the short address by 2 and adding that
value to FE00_H for the SFR register area and adding F000_H for the extended SFR area.
Bit-addressable registers are highlighted in gray.
Users Manual
13 - 13
2000-06-15