SDA6000 Datasheet, PDF (212/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
33 MHz
S0R
Fractional
Divider
÷2
÷3
S0FDE
13-Bit Reload Register
f
÷ 16 ^BR
Baud Rate
Clock
f
MUX ^DIV 13-Bit Baud Rate Timer
f
BRT
Sample
Clock
S0BRS
S0FDE
0
0
1
S0BRS
0
1
X
Selected Divider
÷2
÷3
Fractional Divider
UES11151
Figure 7-32 ASC0 Baud Rate Generator Circuitry in Asynchronous Modes
Using the fixed Input Clock Divider
The baud rate for asynchronous operation of serial channel ASC0, when using the fixed
input clock divider ratios (S0FDE = 0) and the required reload value for a given baud
rate, can be determined by the following formulas:
S0FDE
0
S0BRS
0
1
S0BG
0 … 8191
Formula
33 MHz
Baud rate = _{32 x (S0BG+1)}
S0BG =
33 MHz
32 x Baud rate
-1
33 MHz
Baud rate = _{48 x (S0BG+1)}
S0BG =
33 MHz
48 x Baud rate
-1
S0BG represents the content of the reload register S0BG, taken as an unsigned 13-bit
integer.
The maximum baud rate that can be achieved by the asynchronous modes when using
the two fixed clock dividers and a CPU clock of 33.33 MHz is 1041.66 KBaud. The table
Users Manual
7 - 61
2000-06-15