SDA6000 Datasheet, PDF (170/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
7.1.2 Functional Description of Timer Block 2
Timer block 2 includes the two timers T5 (referred to as the auxiliary timer) and T6
(referred to as the core timer), and the 16-bit capture/reload register CAPREL.
The count direction (Up / Down) may be programmed by software. The auxiliary timer
T6 may be reloaded with the contents of CAPREL.
The toggle bit (T6OTL) also supports the concatenation of T6 with auxiliary timer T5,
while concatenation of T6 with other timers is provided through line T6OFL. Triggered
by an external signal, the contents of T5 can be captured in register CAPREL, and T5
may optionally be cleared. Both timer T6 and T5 can count up or down, and the current
timer value can be read or modified by the CPU in the non-bitaddressable SFRs T5 and
T6.
f _{hw_clk}
2ⁿ : 1
CAPIN
T3IN/
T3EUD
f _{hw_clk}
2ⁿ : 1
T5
Mode
Control
U/D
GPT2 Timer T5
Clear
Capture
MUX
GPT2 CAPREL
CT3
T6
Mode
Control
Clear
GPT2 Timer T6
U/D
Figure 7-14 Structure of Timer Block 2
Users Manual
7 - 19
Interrupt
Request
Interrupt
Request
T6OTL
Interrupt
Request
UES11205
2000-06-15