SDA6000 Datasheet, PDF (17/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Overview
1
Overview
M2 is designed to provide absolute top performance for a wide spectrum of teletext and
graphic applications in standard and high end TV-sets and VCRs. M2 contains a data
caption unit, a display unit and a high performance Infineon C16x based microcontroller
(so that M2 becomes a one chip TV-controller) an up to level 3.5 teletext decoder and
display processor with enhanced graphic accelerator capabilities. It is not only optimized
for teletext usage but also, due to its extremely efficient architecture, can be used as a
universal graphic engine.
M2 is able to support a wide range of standards like PAL, NTSC or applications like
Teletext, VPS, WSS, Chinatext, Closed Caption and EPG (Electronic Program Guide).
With the support of a huge number of variable character sets and graphic capabilities a
wide range of OSD applications are also open for M2.
A new flexible data caption system enables M2 to slice most data, making the IC an
universal data decoder. The digital slicer concept contains measurement circuitries that
help identify bad signal conditions and therefore support the automatic compensation of
the most common signal disturbances. M2’s enhanced data caption control logic allows
individual programming, which means that every line can carry an individual service to
be sliced and stored in the memory.
The display generation of M2 is based on frame buffer technology. A frame buffer
concept displays information which is individually stored for each pixel, allowing greater
flexibility with screen menus. Proportional fonts, asian characters and even HTML
browsers are just some examples of applications that can now be supported.
Thus, with the M2, the process of generation and display of on-screen graphics is split
up into two independent tasks. The generation of the image in the frame buffer is
supported by a hardware graphics accelerator which frees the CPU from power intensive
address calculations. The graphics accelerator ‘prints’ the characters, at the desired
‘screen’ position, into the frame buffer memory based on a display list provided by the
software.
The second part of the display generator (the screen refresh unit) then reads the frame
buffer according to the programmed display mode and screen refresh rate and converts
the pixel information into an analog RGB signal.
Furthermore, M2 has implemented an RGB-DAC for a maximum color resolution of
state-of-the-art up to 65536 colors, so that the complete graphic functionality is
implemented as a system on chip. The screen resolution is programmable up to SVGA,
to cover today’s and tomorrow’s applications, only limited by the available memory
(64 Mbit) and the maximum pixel clock frequency (50 MHz).
The memory architecture is based on the concept of a unified memory - placing program
code, variables, application data, bitmaps and data captured from the analog TV signal’s
vertical blanking interval (VBI) in the same physical memory. M2’s external bus interface
Users Manual
1-3
2000-06-15