SDA6000 Datasheet, PDF (124/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
System Control & Configuration
Chip Select Line
Pin P4.1 (CSENA) defines the external memory configuration. When pulled low it
enables chip select 3 (CS3) (a second ROM device is assumed).
RP0H.1 = ‘0’ denotes the memory configuration with only one ROM device while
RP0H.1 = ‘1’ indicates availability of the 2nd ROM device.
Note: CS3 status cannot be changed via software after reset.
Segment Address Lines
The status of Pins P4.5 … P4.3 (SALSEL) during reset defines the number of active
segment address lines. This allows the selection which pins of Port 4 drive address lines
and which are used for general purpose I/O. The three bits are latched in register RP0H.
Depending on the system architecture the required address space is chosen and
accessible right from the start, so the initialization routine can directly access all
locations without prior programming. The required pins of Port 4 are automatically
switched to address output mode.
During runtime the configured number of segment address line can be read from bit field
RP0H.5 (= SALSEL.2) … RP0H.3 (= SALSEL.0).
SALSEL
111
110
101
100
011
010
001
000
Segment Address Lines
A20, A19, A18, A17, A16
A19, A18, A17, A16
A18, A17, A16
A17, A16
A16
–
–
–
Directly Accessible Address Space
4 MByte (Default without pull-downs)
2 MByte
1 MByte
512 KByte
256 KByte
128 KByte
128 KByte
128 KByte
Default: 5-bit segment address (A20 … A16) allowing access to 4 MByte.
Note: The selected number of segment address lines cannot be changed via software
after reset.
Users Manual
6-7
2000-06-15