SDA6000 Datasheet, PDF (251/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
7.5.1 Operational Overview
Data is transferred by the 2-line I²C bus (SDA, SCL) using a protocol that ensures
reliable and efficient transfers. This protocol clearly distinguishes regular data transfers
from defined control signals which control the data transfers.
The following bus conditions are defined:
Bus Idle:
SDA and SCL remain high. The I²C bus is currently not used.
Data Valid:
SDA stable during the high phase of SCL. SDA then represents the
transferred bit. There is one clock pulse for each transferred bit of data.
During data transfers SDA may only change while SCL is low (see
below)!
Start Transfer: A falling edge on SDA ( ) while SCL is high indicates a start condition.
This start condition initiates a data transfer over the I²C bus.
Stop Transfer: A rising edge on SDA ( ) while SCL is high indicates a stop condition.
This stop condition terminates a data transfer. An arbitrary number of
bytes may be transferred between a start condition and a stop condition.
7.5.2 The Physical I²C-Bus Interface
Communication via the I²C Bus uses two bidirectional lines, the serial data line SDA and
the serial clock line SCL. Each of these two generic interface lines can be connected to
a number of IO port lines. These connections can be established and released under
software control.
Ι²C Module
Generic Data Line
Generic Clock Line
Figure 7-45 I²C Bus Line Connections
SDAx
SDA0
SCL0
SCLx
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Users Manual
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2000-06-15