SDA6000 Datasheet, PDF (247/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
Bit
SSC0PEN
SSC0BEN
SSC0AREN
SSC0MS
SSC0EN
Function
SSC0 Phase Error Enable Bit
0: Ignore phase errors
1: Check phase errors
SSC0 Baud Rate Error Enable Bit
0: Ignore baud rate errors
1: Check baud rate errors
SSC0 Automatic Reset Enable Bit
0: No additional action upon a baud rate error
1: The SSC is automatically reset upon a baud rate error
SSC0 Master Select Bit
0: Slave Mode. Operate on shift clock received via SCLK.
1: Master Mode. Generate shift clock and output it via SCLK.
SSC0 Enable Bit = ‘0’
Transmission and reception disabled. Access to control bits.
Users Manual
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2000-06-15