SDA6000 Datasheet, PDF (256/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
7.5.4 Registers
All available module registers are summarized in the overview table below.
Register
Name
ICCFG
ICCON
ICST
ICADR
ICRTBL
ICRTBH
IICPISEL²⁾
Register Description
I²C Configuration Register
I²C Control Register
I²C Status Register
I²C Address Register
I²C Receive/Transmit Buffer
I²C Receive/Transmit Buffer
I²C Port Input Select Register
1) _{b: bit addressable / p: bit protected}
2) _{Itus currently no function. Should be left on reset value.}
I²C Configuration Register
ICCFG
15 14 13 12 11 10 9 8 7
BRPL
0
Address b/p¹⁾ Reset Value
00’E810_H b
00’E812_H b
00’E814_H b
00’E816_H b
00’E818_H –
00’E81A_H –
00’E804_H b
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
Reset Value: 0000_H
6543210
0
SCL SCL
EN1 EN0
0
SDA SDA SDA
EN2 EN1 EN0
Field
SDAENx
(x = 2 … 0)
SCLENx
(x = 3 … 0)
BRPL
Bits
2…0
5…4
15 … 8
Type
rw
rw
rw
Value Description
Enable Input for Data Pin x
These bits determine to which pins the I²C data
line is connected.
0
SDA pin x is disconnected.
1
SDA pin x is connected with I²C data line.
Enable Input for Clock Pin x
These bits determine to which pins the I²C
clock line is connected.
0
SCL pin x is disconnected.
1
SCL pin x is connected with I²C clock line.
–
Baud rate Prescaler Low
Determines the 8 least significant bits of the 10
bit baud rate prescaler. (See BPRH in ICADR.)
Users Manual
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2000-06-15