SDA6000 Datasheet, PDF (234/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
Ports & Direction Control
Alternate Functions
ODP3
DP3
P3
SLCK/P3.13
MTSR/P3.9
MRST/P3.8
Data Registers
SSCBR
SSCTB
SSCRB
ODP3 Port 3 Open Drain Control Register
DP3 Port 3 Direction Control Register
SSCBR SSC Baud Rate Generator/Reload Register
SSCTB SSC Transmit Buffer Register (write only)
SSCTIC SSC Transmit Interrupt Control Register
Control Registers
SSCCON
Interrupt Control
SSCTIC
SSCRIC
SSCEIC
P3
Port 3 Data Register
SSCCON SSC Control Register
SSCRB SSC Receive Buffer Register (read only)
SSCRIC SSC Receive Interrupt Control Register
SSCEIC SSC Error Interrupt Control Register
UEA11157
Figure 7-38 SFRs and Port Pins Associated with the SSC0
The SSC0 supports full-duplex and half-duplex synchronous communication up to
16.5 MBaud (@ 33.33 MHz module clock). The serial clock signal can be generated by
the SSC0 itself (master mode), or received from an external master (slave mode). Data
width, shift direction, clock polarity and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data is
double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial
clock signal.
The high-speed synchronous serial interface can be configured in a very flexible way, so
it can be used with other synchronous serial interfaces, serve for master/slave or
multimaster interconnections or operate compatible with the popular SPI interface. So it
can be used to communicate with shift registers (I/O expansion), peripherals (e.g.
EEPROMs etc.) or other controllers (networking). The SSC0 supports half-duplex and
full-duplex communication. Data is transmitted or received on pins MTSR0 (Master
Transmit/Slave Receive) and MRST0 (Master Receive/Slave Transmit). The clock
signal is output or input on pin SCLK0. These pins are alternate functions of port pins.
Users Manual
7 - 83
2000-06-15