C8051F124-GQR Datasheet, PDF (97/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 7.3. ADC2CF: ADC2 Configuration
SFR Page: 2
SFR Address: 0xBC
R/W
R/W
AD2SC4 AD2SC3
Bit7
Bit6
R/W
AD2SC2
Bit5
R/W
AD2SC1
Bit4
R/W
AD2SC0
Bit3
R/W
R/W
R/W
Reset Value
- AMP2GN1 AMP2GN0 11111000
Bit2
Bit1
Bit0
Bits7–3:
AD2SC4–0: ADC2 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD2SC refers to the 5-bit value held in AD2SC4–0, and CLK_SAR2 refers to the desired
ADC2 SAR clock (Note: the ADC2 SAR Conversion Clock should be less than or equal to
6 MHz).
AD2SC = -^S---^Y----^S---^C-----^L---^K--- – 1
CLK_SAR2
Bit2:
Bits1–0:
UNUSED. Read = 0b; Write = don’t care.
AMP2GN1–0: ADC2 Internal Amplifier Gain (PGA).
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
Rev. 1.4
97