C8051F124-GQR Datasheet, PDF (235/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
18. Port Input/Output
The devices are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins (100-pin
TQFP packaging) or 32 digital I/O pins (64-pin TQFP packaging), organized as 8-bit Ports. All ports are
both bit- and byte-addressable through their corresponding Port Data registers. All Port pins are 5 V-toler-
ant, and all support configurable Open-Drain or Push-Pull output modes and weak pullups. A block dia-
gram of the Port I/O cell is shown in Figure 18.1. Complete Electrical Specifications for the Port I/O pins
are given in Table 18.1.
/WEAK-PULLUP
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
VDD
VDD
(WEAK)
PORT
PAD
ANALOG INPUT
PORT-INPUT
Analog Select
(Ports 1, 2, and 3)
DGND
Figure 18.1. Port I/O Cell Block Diagram
Rev. 1.4
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