C8051F124-GQR Datasheet, PDF (114/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
REF0CN
External
Voltage
Reference
Circuit
VDD
R1
DGND
VREF2
VREF0
AV+
1
0
0
ADC2
Ref
ADC0
Ref
1
VREFD
DAC0
Ref
+
4.7F
VREF
0.1F
Recommended Bypass
Capacitors
DAC1
x2
REFBE
BIASE
EN
1.2V
Band-Gap
Bias to
ADCs,
DACs
Figure 9.1. Voltage Reference Functional Block Diagram (C8051F120/2/4/6)
SFR Definition 9.1. REF0CN: Reference Control (C8051F120/2/4/6)
SFR Page: 0
SFR Address: 0xD1
R/W
R/W
-
-
Bit7
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
AD0VRS AD2VRS TEMPE BIASE REFBE 00000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
UNUSED. Read = 000b; Write = don’t care.
AD0VRS: ADC0 Voltage Reference Select.
0: ADC0 voltage reference from VREF0 pin.
1: ADC0 voltage reference from DAC0 output.
AD2VRS: ADC2 Voltage Reference Select.
0: ADC2 voltage reference from VREF2 pin.
1: ADC2 voltage reference from AV+.
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor Off.
1: Internal Temperature Sensor On.
BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC, DAC, or VREF).
0: Internal Bias Generator Off.
1: Internal Bias Generator On.
REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer Off.
1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin.
114
Rev. 1.4