C8051F124-GQR Datasheet, PDF (297/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 21.2. SSTA0: UART0 Status and Clock Selection
R/W
FE0
Bit7
R/W
RXOV0
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
TXCOL0 SMOD0 S0TCLK1 S0TCLK0 S0RCLK1 S0RCLK0 00000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x91
SFR Page: 0
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–2:
.
FE0: Frame Error Flag.*
This flag indicates if an invalid (low) STOP bit is detected.
0: Frame Error has not been detected
1: Frame Error has been detected.
RXOV0: Receive Overrun Flag.*
This flag indicates new data has been latched into the receive buffer before software has
read the previous byte.
0: Receive overrun has not been detected.
1: Receive Overrun has been detected.
TXCOL0: Transmit Collision Flag.*
This flag indicates user software has written to the SBUF0 register while a transmission is
in progress.
0: Transmission Collision has not been detected.
1: Transmission Collision has been detected.
SMOD0: UART0 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART0 baud rate logic for config-
urations described in the UART0 section.
0: UART0 baud rate divide-by-two enabled.
1: UART0 baud rate divide-by-two disabled.
UART0 Transmit Baud Rate Clock Selection Bits
S0TCLK1
0
0
1
1
S0TCLK0
0
1
0
1
Serial Transmit Baud Rate Clock Source
Timer 1 generates UART0 TX Baud Rate
Timer 2 Overflow generates UART0 TX baud rate
Timer 3 Overflow generates UART0 TX baud rate
Timer 4 Overflow generates UART0 TX baud rate
Bits1–0: UART0 Receive Baud Rate Clock Selection Bits
*Note:
S0RCLK1
0
0
1
1
S0RCLK0
0
1
0
1
Serial Receive Baud Rate Clock Source
Timer 1 generates UART0 RX Baud Rate
Timer 2 Overflow generates UART0 RX baud rate
Timer 3 Overflow generates UART0 RX baud rate
Timer 4 Overflow generates UART0 RX baud rate
FE0, RXOV0, and TXCOL0 are flags only, and no interrupt is generated by these conditions.
Rev. 1.4
297