C8051F124-GQR Datasheet, PDF (195/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 14.8. PLL0FLT: PLL Filter
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
-
-
PLLICO1 PLLICO0 PLLLP3 PLLLP2 PLLLP1 PLLLP0 00110001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x8F
SFR Page: F
Bits 7–6: UNUSED: Read = 00b; Write = don’t care.
Bits 5–4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.
Selection is based on the desired output frequency, according to the following table:
PLL Output Clock
65–100 MHz
45–80 MHz
30–60 MHz
25–50 MHz
PLLICO1-0
00
01
10
11
Bits 3–0: PLLLP3-0: PLL Loop Filter Control Bits.
Selection is based on the divided PLL reference clock, according to the following table:
Divided PLL Reference Clock
19–30 MHz
12.2–19.5 MHz
7.8–12.5 MHz
5–8 MHz
PLLLP3-0
0001
0011
0111
1111
Table 14.2. PLL Frequency Characteristics
–40 to +85 °C unless otherwise specified
Parameter
Conditions
Min Typ
Input Frequency
5
(Divided Reference Frequency)
PLL Output Frequency
25
*Note: The maximum operating frequency of the C8051F124/5/6/7 is 50 MHz
Max
30
100*
Units
MHz
MHz
Rev. 1.4
195