C8051F124-GQR Datasheet, PDF (171/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 12.2. MAC0STA: MAC0 Status
R
R
R
R
R/W
R/W
R/W
R/W Reset Value
-
-
-
-
MAC0HO MAC0Z MAC0SO MAC0N 00000100
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0xC0
SFR Page: 3
Bits 7–4: UNUSED: Read = 0000b, Write = don’t care.
Bit 3: MAC0HO: Hard Overflow Flag.
This bit is set to ‘1’ whenever an overflow out of the MAC0OVR register occurs during a
MAC operation (i.e. when MAC0OVR changes from 0x7F to 0x80 or from 0x80 to 0x7F).
The hard overflow flag must be cleared in software by directly writing it to ‘0’, or by resetting
the MAC logic using the MAC0CA bit in register MAC0CF.
Bit 2: MAC0Z: Zero Flag.
This bit is set to ‘1’ if a MAC0 operation results in an Accumulator value of zero. If the result
is non-zero, this bit will be cleared to ‘0’.
Bit 1: MAC0SO: Soft Overflow Flag.
This bit is set to ‘1’ when a MAC operation causes an overflow into the sign bit (bit 31) of the
MAC0 Accumulator. If the overflow condition is corrected after a subsequent MAC opera-
tion, this bit is cleared to ‘0’.
Bit 0: MAC0N: Negative Flag.
If the MAC Accumulator result is negative, this bit will be set to ‘1’. If the result is positive or
zero, this flag will be cleared to ‘0’.
*Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 12.3. MAC0AH: MAC0 A High Byte
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xC2
SFR Page: 3
Bits 7–0: High Byte (bits 15–8) of MAC0 A Register.
Rev. 1.4
171