C8051F124-GQR Datasheet, PDF (71/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Input Voltage
(AD0.0 - AD0.1)
REF x (2047/2048)
ADC Data
Word
0x7FF0
AD0WINT
not affected
REF x (256/2048)
REF x (-1/2048)
0x1010
0x1000
0x0FF0
0x0000
0xFFF0
0xFFE0
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
Input Voltage
(AD0.0 - AD0.1)
REF x (2047/2048)
ADC Data
Word
0x7FF0
AD0WINT=1
REF x (256/2048)
REF x (-1/2048)
0x1010
0x1000
0x0FF0
0x0000
0xFFF0
0xFFE0
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT
not affected
-REF
0x8000
Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = ‘1’,
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0xFFF0.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x1000 and > 0xFFF0. (2s-complement
math.)
AD0WINT=1
-REF
0x8000
Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = ‘1’,
ADC0LTH:ADC0LTL = 0xFFF0,
ADC0GTH:ADC0GTL = 0x1000.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0xFFF0 or > 0x1000. (2s-complement math.)
Figure 5.9. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data
Rev. 1.4
71