C8051F124-GQR Datasheet, PDF (45/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 4.1. Pin Definitions (Continued)
Name
AD0/D0/P3.0
AD1/D1/P3.1
AD2/D2/P3.2
AD3/D3/P3.3
AD4/D4/P3.4
AD5/D5/P3.5
AD6/D6/P3.6
AD7/D7/P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
Pin Numbers
‘F120
‘F122
‘F124
‘F126
‘F121
‘F123
‘F125
‘F127
‘F130
‘F132
‘F131
‘F133
Type
Description
54 47 54 47 D I/O Bit 0 External Memory Address/Data bus (Multi-
plexed mode)
Bit 0 External Memory Data bus (Non-multi-
plexed mode)
Port 3.0
See Port Input/Output section for complete
description.
53 46 53 46 D I/O Port 3.1. See Port Input/Output section for com-
plete description.
52 45 52 45 D I/O Port 3.2. See Port Input/Output section for com-
plete description.
51 44 51 44 D I/O Port 3.3. See Port Input/Output section for com-
plete description.
50 43 50 43 D I/O Port 3.4. See Port Input/Output section for com-
plete description.
49 42 49 42 D I/O Port 3.5. See Port Input/Output section for com-
plete description.
48 39 48 39 D I/O Port 3.6. See Port Input/Output section for com-
plete description.
47 38 47 38 D I/O Port 3.7. See Port Input/Output section for com-
plete description.
98
98
D I/O Port 4.0. See Port Input/Output section for com-
plete description.
97
97
D I/O Port 4.1. See Port Input/Output section for com-
plete description.
96
96
D I/O Port 4.2. See Port Input/Output section for com-
plete description.
95
95
D I/O Port 4.3. See Port Input/Output section for com-
plete description.
94
94
D I/O Port 4.4. See Port Input/Output section for com-
plete description.
Rev. 1.4
45