C8051F124-GQR Datasheet, PDF (334/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
24.2.6. 16-Bit Pulse Width Modulator Mode
Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare
module defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter
matches the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is
asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA0 CCFn
match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the
PCA0CPMn register. For a varying duty cycle, CCFn should also be set to logic 1 to enable match inter-
rupts. The duty cycle for 16-Bit PWM Mode is given by Equation 24.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Equation 24.3. 16-Bit PWM Duty Cycle
DutyCycle = ^---6---5---5---3---6----–-----^P----^C----^A----0----^C----^P----ⁿ----^
65536
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOPP TGMC
1 MPN n n n F
6nnn
n
n
1 0000 0
PCA0CPHn PCA0CPLn
Enable
16-bit Comparator
match
SET
SQ
CEXn _Crossbar
PCA Timebase
RQ
CLR
PCA0H
PCA0L
Overflow
Figure 24.9. PCA 16-Bit PWM Mode
Port I/O
334
Rev. 1.4