C8051F124-GQR Datasheet, PDF (187/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
14.2. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/
resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 14.1. In RC,
capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 and/or XTAL1
pin(s) as shown in Option 2, 3, or 4 of Figure 14.1. The type of external oscillator must be selected in the
OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Defini-
tion 14.4).
14.3. System Clock Selection
The CLKSL1-0 bits in register CLKSEL select which oscillator source generates the system clock.
CLKSL1-0 must be set to ‘01’ for the system clock to run from the external oscillator; however the external
oscillator may still clock certain peripherals, such as the timers and PCA, when the internal oscillator or the
PLL is selected as the system clock. The system clock may be switched on-the-fly between the internal
and external oscillators or the PLL, so long as the selected oscillator source is enabled and settled. The
internal oscillator requires little start-up time, and may be enabled and selected as the system clock in the
same write to OSCICN. External crystals and ceramic resonators typically require a start-up time before
they are settled and ready for use as the system clock. The Crystal Valid Flag (XTLVLD in register
OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a false
XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and
checking XTLVLD. RC and C modes typically require no startup time. The PLL also requires time to lock
onto the desired frequency, and the PLL Lock Flag (PLLLCK in register PLL0CN) is set to ‘1’ by hardware
once the PLL is locked on the correct frequency.
Rev. 1.4
187