C8051F124-GQR Datasheet, PDF (156/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 11.4. Interrupt Summary (Continued)
Interrupt Source
Interru
pt
Vector
Priority
Order
Pending Flags
Enable Priority
Flag
Control
Comparator 1 Rising Edge 0x006B 13 CP1RIF (CPT1CN.5) Y
2
ECP1R
(EIE1.7)
PCP1F
(EIP1.7)
Timer 3
0x0073
14
TF3 (TMR3CN.7)
EXF3 (TMR3CN.6)
Y
1
ET3
(EIE2.0)
PT3
(EIP2.0)
ADC0 End of Conversion 0x007B 15 AD0INT (ADC0CN.5) Y
0
EADC0
(EIE2.1)
PADC0
(EIP2.1)
Timer 4
0x0083
16
TF4 (TMR4CN.7)
EXF4 (TMR4CN.7)
Y
2
ET4
(EIE2.2)
PT4
(EIP2.2)
ADC2 Window Comparator 0x008B
17
AD2WINT
(ADC2CN.0)
Y
2
EWADC2
(EIE2.3)
PWADC2
(EIP2.3)
ADC2 End of Conversion 0x0093 18 AD2INT (ADC2CN.5) Y
2
EADC2
(EIE2.4)
PADC2
(EIP2.4)
RESERVED
0x009B 19 N/A
N/A N/A N/A N/A
N/A
UART1
0x00A3
20
RI1 (SCON1.0)
TI1 (SCON1.1)
Y
1
ES1
(EIE2.6)
PS1
(EIP2.6)
11.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its
priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 11.4.
11.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is
5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. Additional clock cycles will be required if a cache miss occurs (see Section “16. Branch Target
Cache” on page 211 for more details). If an interrupt is pending when a RETI is executed, a single instruc-
tion is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum
response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of
greater priority) is when the CPU is performing an RETI instruction followed by a DIV as the next instruc-
tion, and a cache miss event also occurs. If the CPU is executing an ISR for an interrupt with equal or
higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI
and following instruction.
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Rev. 1.4