C8051F124-GQR Datasheet, PDF (304/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 22.1. SCON1: Serial Port 1 Control
R/W
R/W
S1MODE
-
Bit7
Bit6
R/W
MCE1
Bit5
R/W
REN1
Bit4
R/W
TB81
Bit3
R/W
RB81
Bit2
R/W
R/W
Reset Value
TI1
RI1 01000000
Bit1
Bit0
Bit
Addressable
SFR Address: 0x98
SFR Page: 1
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
S1MODE: Serial Port 1 Operation Mode.
This bit selects the UART1 Operation Mode.
0: Mode 0: 8-bit UART with Variable Baud Rate
1: Mode 1: 9-bit UART with Variable Baud Rate
UNUSED. Read = 1b. Write = don’t care.
MCE1: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI1 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI1 is set and an interrupt is generated only when the ninth bit is logic 1.
REN1: Receive Enable.
This bit enables/disables the UART receiver.
0: UART1 reception disabled.
1: UART1 reception enabled.
TB81: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It
is not used in 8-bit UART Mode. Set or cleared by software as required.
RB81: Ninth Receive Bit.
RB81 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
TI1: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in 8-
bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART1
interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt service
routine. This bit must be cleared manually by software
RI1: Receive Interrupt Flag.
Set to ‘1’ by hardware when a byte of data has been received by UART1 (set at the STOP bit
sampling time). When the UART1 interrupt is enabled, setting this bit to ‘1’ causes the CPU
to vector to the UART1 interrupt service routine. This bit must be cleared manually by soft-
ware.
304
Rev. 1.4