C8051F124-GQR Datasheet, PDF (343/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 25.1. Boundary Data Register Bit Definitions (Continued)
Bit
Action Target
103, 105, 107, Capture P6.n input from pin
109, 111, 113, 115, _{Update P6.n output to pin}
117
118, 120, 122, Capture P7.n output enable from MCU
124, 126, 128, Update P7.n output enable to pin
130, 132
119, 121, 123, Capture P7.n input from pin
125, 127, 129, _{Update P7.n output to pin}
131, 133
25.1.1. EXTEST Instruction
The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all
the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.
25.1.2. SAMPLE Instruction
The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of
the scan-path latches.
25.1.3. BYPASS Instruction
The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data reg-
ister.
25.1.4. IDCODE Instruction
The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.
JTAG Register Definition 25.2. DEVICEID: JTAG Device ID
Reset Value
Version
Part Number
Manufacturer ID
1
0xn0003243
Bit31
Bit28 Bit27
Bit12 Bit11
Bit1 Bit0
Version = 0000b
Part Number = 0000 0000 0000 0111b (C8051F120/1/2/3/4/5/6/7 or C8051F130/1/2/3)
Manufacturer ID = 0010 0100 001b (Silicon Labs)
Rev. 1.4
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