C8051F124-GQR Datasheet, PDF (249/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 18.6. P1: Port1 Data
R/W
P1.7
Bit7
R/W
P1.6
Bit6
R/W
P1.5
Bit5
R/W
P1.4
Bit4
R/W
P1.3
Bit3
R/W
P1.2
Bit2
R/W
P1.1
Bit1
R/W
Reset Value
P1.0 11111111
Bit0
Bit
Addressable
SFR Address: 0x90
SFR Page: All Pages
Bits7–0:
P1.[7:0]: Port1 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
Notes:
1. On C8051F12x devices, P1.[7:0] can be configured as inputs to ADC2 as AIN2.[7:0], in which
case they are ‘skipped’ by the Crossbar assignment process and their digital input paths are
disabled, depending on P1MDIN (See SFR Definition 18.7). Note that in analog mode, the
output mode of the pin is determined by the Port 1 latch and P1MDOUT (SFR Definition 18.8).
See Section “7. ADC2 (8-Bit ADC, C8051F12x Only)” on page 91 for more information
about ADC2.
2. P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-
multiplexed mode). See Section “17. External Data Memory Interface and On-Chip
XRAM” on page 219 for more information about the External Memory Interface.
SFR Definition 18.7. P1MDIN: Port1 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xAD
SFR Page: F
Bits7–0:
P1MDIN.[7:0]: Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from
the Port bit will always return ‘0’). The weak pullup on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic
level at the Pin. When configured as a digital input, the state of the weak pullup for the port
pin is determined by the WEAKPUD bit (XBR2.7, see SFR Definition 18.3).
Rev. 1.4
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