C8051F124-GQR Datasheet, PDF (146/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 11.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
SFR
Page
Description
ACC
0xE0 All Pages Accumulator
ADC0CF
0xBC
0 ADC0 Configuration
ADC0CN
0xE8
0 ADC0 Control
ADC0GTH
0xC5
0 ADC0 Greater-Than High Byte
ADC0GTL
0xC4
0 ADC0 Greater-Than Low Byte
ADC0H
0xBF
0 ADC0 Data Word High Byte
ADC0L
0xBE
0 ADC0 Data Word Low Byte
ADC0LTH
0xC7
0 ADC0 Less-Than High Byte
ADC0LTL
0xC6
0 ADC0 Less-Than Low Byte
ADC2
0xBE
2 ADC2 Data Word
ADC2CF
0xBC
2 ADC2 Configuration
ADC2CN
0xE8
2 ADC2 Control
ADC2GT
0xC4
2 ADC2 Greater-Than
ADC2LT
0xC6
2 ADC2 Less-Than
AMX0CF
0xBA
0 ADC0 Multiplexer Configuration
AMX0SL
0xBB
0 ADC0 Multiplexer Channel Select
AMX2CF
0xBA
2 ADC2 Multiplexer Configuration
AMX2SL
0xBB
2 ADC2 Multiplexer Channel Select
B
CCH0CN
CCH0LC
CCH0MA
CCH0TN
CKCON
CLKSEL
CPT0CN
CPT0MD
CPT1CN
CPT1MD
0xF0
0xA1
0xA3
0x9A
0xA2
0x8E
0x97
0x88
0x89
0x88
0x89
All Pages B Register
F Cache Control
F Cache Lock
F Cache Miss Accumulator
F Cache Tuning
0 Clock Control
F System Clock Select
1 Comparator 0 Control
1 Comparator 0 Configuration
2 Comparator 1 Control
2 Comparator 1 Configuration
DAC0CN
0xD4
0 DAC0 Control
DAC0H
0xD3
0 DAC0 High Byte
DAC0L
0xD2
0 DAC0 Low Byte
DAC1CN
0xD4
1 DAC1 Control
DAC1H
0xD3
1 DAC1 High Byte
DAC1L
0xD2
1 DAC1 Low Byte
DPH
DPL
0x83
0x82
All Pages Data Pointer High Byte
All Pages Data Pointer Low Byte
Page No.
page 153
page 62¹, page 80²
page 63¹, page 81²
page 66¹, page 84²
page 66¹, page 84²
page 64¹, page 82²
page 64¹, page 82²
page 67¹, page 85²
page 67¹, page 85²
page 99³
page 97³
page 98³
page 102³
page 102³
page 60¹, page 78²
page 61¹, page 79²
page 95³
page 96³
page 153
page 215
page 216
page 217
page 216
page 315
page 188
page 123
page 123
page 124
page 125
page 108³
page 107³
page 107³
page 110³
page 109³
page 109³
page 151
page 151
146
Rev. 1.4