C8051F124-GQR Datasheet, PDF (43/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 4.1. Pin Definitions (Continued)
Pin Numbers
Name
‘F120
‘F122
‘F124
‘F126
‘F121
‘F123
‘F125
‘F127
‘F130
‘F132
‘F131
‘F133
Type
Description
DAC1
99 63
A Out Digital to Analog Converter 1 Voltage Output.
(See DAC Specification for complete descrip-
tion).
P0.0
62 55 62 55 D I/O Port 0.0. See Port Input/Output section for com-
plete description.
P0.1
61 54 61 54 D I/O Port 0.1. See Port Input/Output section for com-
plete description.
P0.2
60 53 60 53 D I/O Port 0.2. See Port Input/Output section for com-
plete description.
P0.3
59 52 59 52 D I/O Port 0.3. See Port Input/Output section for com-
plete description.
P0.4
58 51 58 51 D I/O Port 0.4. See Port Input/Output section for com-
plete description.
ALE/P0.5
57 50 57 50 D I/O ALE Strobe for External Memory Address bus
(multiplexed mode)
Port 0.5
See Port Input/Output section for complete
description.
RD/P0.6
56 49 56 49 D I/O /RD Strobe for External Memory Address bus
Port 0.6
See Port Input/Output section for complete
description.
WR/P0.7
55 48 55 48 D I/O /WR Strobe for External Memory Address bus
Port 0.7
See Port Input/Output section for complete
description.
AIN2.0/A8/P1.0 36 29 36 29 A In ADC2 Input Channel 0 (See ADC2 Specification
D I/O for complete description).
Bit 8 External Memory Address bus (Non-multi-
plexed mode)
Port 1.0
See Port Input/Output section for complete
description.
AIN2.1/A9/P1.1 35 28 35 28 A In Port 1.1. See Port Input/Output section for com-
D I/O plete description.
Rev. 1.4
43