C8051F124-GQR Datasheet, PDF (139/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

SFRPAGE
pushed to
SFRNEXT
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Page 0x02
Automatically
pushed on stack in
SFRPAGE on ADC2
interrupt
0x02
(ADC2)
0x0F
(Port 5)
SFRPAGE
SFRNEXT
SFRLAST
Figure 11.6. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs
While in the ADC2 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the ADC2 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to
access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that
was in the SFRPAGE register before the PCA interrupt (SFR Page 2 for ADC2) is pushed down the stack
into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in this
case SFR Page 0x0F for Port 5) is pushed down to the SFRLAST register, the “bottom” of the stack. Note
that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be overwritten.
See Figure 11.7 below.
Rev. 1.4
139