C8051F124-GQR Datasheet, PDF (193/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
page 199). Important Note: Cache reads, cache writes, and the prefetch engine
should be disabled whenever the FLRT bits are changed to a lower setting.
To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external
clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’.
Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and
PLLPWR bits can be cleared at the same time.
SFR Definition 14.5. PLL0CN: PLL Control
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W Reset Value
-
-
-
PLLLCK
0
PLLSRC PLLEN PLLPWR 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x89
SFR Page: F
Bits 7–5: UNUSED: Read = 000b; Write = don’t care.
Bit 4: PLLCK: PLL Lock Flag.
0: PLL Frequency is not locked.
1: PLL Frequency is locked.
Bit 3: RESERVED. Must write to ‘0’.
Bit 2: PLLSRC: PLL Reference Clock Source Select Bit.
0: PLL Reference Clock Source is Internal Oscillator.
1: PLL Reference Clock Source is External Oscillator.
Bit 1: PLLEN: PLL Enable Bit.
0: PLL is held in reset.
1: PLL is enabled. PLLPWR must be ‘1’.
Bit 0: PLLPWR: PLL Power Enable.
0: PLL bias generator is de-activated. No static power is consumed.
1: PLL bias generator is active. Must be set for PLL to operate.
Rev. 1.4
193