C8051F124-GQR Datasheet, PDF (242/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
P0
P1
P2
P3
Crossbar Register Bits
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
TX0
●
RX0
●
UART0EN: XBR0.2
SCK
●●
MISO
MOSI
●●
●●
SPI0EN: XBR0.1
NSS
●●
NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
SDA
● ●●●●
SCL
● ●●●
●
●●
SMB0EN: XBR0.0
TX1
● ●●●●
RX1
● ●●●
●●●
●●●●
UART1EN: XBR2.2
CEX0
●
●●●●
●●●●●
CEX1
● ●●●
●●●●●●
CEX2
CEX3
● ●●
●●
●●●●●●●
●●●●●●●●
PCA0ME: XBR0.[5:3]
CEX4
●
●●●●●●●●●
CEX5
●
●●●●●●●●●
ECI
●●●●●●
●●●●●●●●●●●
ECI0E: XBR0.6
CP0
●●●●●●
●●●●●●●●●●●●
CP0E: XBR0.7
CP1
●●●●●●
●●●●●●●●●●●●●
CP1E: XBR1.0
T0
●●●●●●
●●●●●●●●●●●●●●
T0E: XBR1.1
/INT0
●●●●●●
●●●●●●●●●●●●●●●
INT0E: XBR1.2
T1
●●●●●●
●●●●●●●●●●●●●●●●
T1E: XBR1.3
/INT1
●●●●●●
●●●●●●●●●●●●●●●●●
INT1E: XBR1.4
T2
●●●●●●
●●●●●●●●●●●●●●●●●●
T2E: XBR1.5
T2EX ● ● ● ● ● ●
●●●●●●●●●●●●●●●●●●●
T2EXE: XBR1.6
T4
●●●●●●
●●●●●●●●●●●●●●●●●●●●
T4E: XBR2.3
T4EX ● ● ● ● ● ●
●●●●●●●●●●●●●●●●●●●●●
T4EXE: XBR2.4
/SYSCLK ● ● ● ● ● ●
●●●●●●●●●●●●●●●●●●●●●●
SYSCKE: XBR1.7
CNVSTR0 ● ● ● ● ● ●
●●●●●●●●●●●●●●●●●●●●●●●
CNVSTE0: XBR2.0
CNVSTR2 ● ● ● ● ● ●
● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● CNVSTE2: XBR2.5
AIN2 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L Muxed Data/Non-muxed Data
Figure 18.5. Priority Crossbar Decode Table (EMIFLE = 1; EMIF in Non-Multiplexed
Mode; P1MDIN = 0xFF)
242
Rev. 1.4