C8051F124-GQR Datasheet, PDF (177/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
13. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
• CIP-51 halts program execution.
• Special Function Registers (SFRs) are initialized to their defined reset values.
• External port pins are forced to a known configuration.
• Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pullups during and after the
reset. For V_DD Monitor resets, the RST pin is driven low until the end of the V_DD reset timeout.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator running at its lowest frequency. Refer to Section “14. Oscillators” on page 185 for informa-
tion on selecting and configuring the system clock source. The Watchdog Timer is enabled using its
longest timeout interval (see Section “13.7. Watchdog Timer Reset” on page 179). Once the system clock
source is stable, program execution begins at location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on, power-fail, external RST pin,
external CNVSTR0 signal, software command, Comparator0, Missing Clock Detector, and Watchdog
Timer. Each reset source is described in the following sections.
VDD
(Port
I/O)
CP0+
CP0-
XTAL1
XTAL2
Crossbar
CNVSTR
(CNVSTR
reset
enable)
Comparator0
+
-
(CP0
reset
enable)
Supply
Monitor
+
-
Supply
Reset
Timeout
Internal
Clock
Generator
PLL
Circuitry
OSC
Missing
Clock
Detector
(one-
shot)
EN
WDT
EN PRE
System
Clock
Clock Select
CIP-51
Software Reset
Microcontroller
Core
System Reset
Extended Interrupt
Handler
Figure 13.1. Reset Sources
(wired-OR)
Reset
Funnel
/RST
Rev. 1.4
177