C8051F124-GQR Datasheet, PDF (329/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 24.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
PWM16 ECOM CAPP CAPN MAT
X
X
1
0
0
X
X
0
1
0
X
X
1
1
0
X
1
0
0
1
X
1
0
0
1
X
1
0
0
0
0
1
0
0
0
1
1
0
0
0
X = Don’t Care
TOG
0
0
0
0
1
1
0
0
PWM
0
0
0
0
0
1
1
1
ECCF
Operation Mode
X
Capture triggered by positive edge
on CEXn
X
Capture triggered by negative
edge on CEXn
X
Capture triggered by transition on
CEXn
X
Software Timer
X
High Speed Output
X
Frequency Output
0
8-Bit Pulse Width Modulator
0
16-Bit Pulse Width Modulator
24.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software.
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
PCA Interrupt
PCA0CN
CCCCCCCC
FRCCCCCC
FFFFFF
543210
Port I/O
Crossbar ^CEXn
0
1
0
1
PCA0CPLn PCA0CPHn
Capture
PCA
Timebase
PCA0L
PCA0H
Figure 24.4. PCA Capture Mode Diagram
Note: The signal at CEXn must be high or low for at least 2 system clock cycles in order to be valid.
Rev. 1.4
329