C8051F124-GQR Datasheet, PDF (282/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate
R/W
SCR7
Bit7
R/W
SCR6
Bit6
R/W
SCR5
Bit5
R/W
SCR4
Bit4
R/W
SCR3
Bit3
R/W
SCR2
Bit2
R/W
SCR1
Bit1
R/W
Reset Value
SCR0 00000000
Bit0
SFR Address: 0x9D
SFR Page: 0
Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
f_SCK
=
-------------S---Y----S----C----L---K---------------
2  SPI0CKR + 1
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f_SCK = _{2---2--}-0---0-_--40---0--+-0---0-1---_
f_SCK = 200kHz
SFR Definition 20.4. SPI0DAT: SPI0 Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x9B
SFR Page: 0
Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
282
Rev. 1.4