C8051F124-GQR Datasheet, PDF (31/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.4. 16 x 16 MAC (Multiply and Accumulate) Engine
The C8051F120/1/2/3 and C8051F130/1/2/3 devices include a multiply and accumulate engine which can
be used to speed up many mathematical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit
adder, which can perform integer or fractional multiply-accumulate and multiply operations on signed input
values in two SYSCLK cycles. A rounding engine provides a rounded 16-bit fractional result after an addi-
tional (third) SYSCLK cycle. MAC0 also contains a 1-bit arithmetic shifter that will left or right-shift the con-
tents of the 40-bit accumulator in a single SYSCLK cycle.
MAC0 A Register
MAC0AH MAC0AL
MAC0 B Register
MAC0BH MAC0BL
MAC0FM _{16 x 16 Multiply}
40 bit Add
MAC0MS
1
0
0
MAC0 Accumulator
MAC0OVR MAC0ACC3 MAC0ACC2 MAC0ACC1 MAC0ACC0
1 bit Shift
Rounding Engine
Flag Logic
MAC0 Rounding Register
MAC0RNDH MAC0RNDL
MAC0CF
MAC0STA
Figure 1.10. MAC0 Block Diagram
Rev. 1.4
31