C8051F124-GQR Datasheet, PDF (322/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 23.9. TMRnCF: Timer 2, 3, and 4 Configuration
R/W
R/W
-
-
-
TnM1 TnM0
Bit7
Bit6
Bit5
Bit4
Bit3
SFR Address: TMR2CF:0xC9;TMR3CF:0xC9;TMR4CF:0xC9
SFR Page TMR2CF: page 0;TMR3CF: page 1;TMR4CF: Page 2
R/W
TOGn
Bit2
R/W
TnOE
Bit1
R/W
DCENn
Bit0
Reset Value
00000000
Bit7–5:
Bit4–3:
Bit2:
Bit1:
Bit0:
Reserved.
TnM1 and TnM0: Timer Clock Mode Select Bits.
Bits used to select the Timer clock source. The sources can be the System Clock
(SYSCLK), SYSCLK divided by 2 or 12, or the external clock divided by 8. Clock source is
selected as follows:
00: SYSCLK/12
01: SYSCLK
10: EXTERNAL CLOCK/8 (Synchronized to the System Clock)
11: SYSCLK/2
TOGn: Toggle output state bit.
When timer is used to toggle a port pin, this bit can be used to read the state of the output, or
can be written to in order to force the state of the output (Timer 2 and Timer 4 Only).
TnOE: Timer output enable bit.
This bit enables the timer to output a 50% duty cycle output to the timer’s assigned external
port pin.
NOTE: A timer is configured for Square Wave Output as follows:
CP/RLn = 0
C/Tn = 0
TnOE = 1
Load RCAPnH:RCAPnL (See “Square Wave Frequency (Timer 2 and Timer 4 Only)” on
page 320.)
Configure Port Pin to output squarewave (See Section “18. Port Input/Output” on
page 235)
0: Output of toggle mode not available at Timers’s assigned port pin.
1: Output of toggle mode available at Timers’s assigned port pin.
DCENn: Decrement Enable Bit.
This bit enables the timer to count up or down as determined by the state of TnEX.
0: Timer will count up, regardless of the state of TnEX.
1: Timer will count up or down depending on the state of TnEX as follows:
if TnEX = 0, the timer counts DOWN.
if TnEX = 1, the timer counts UP.
Note: Timer 3 and Timer 2 share the T2 and T2EX pins.
322
Rev. 1.4